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Hardware Reference Manual for i.MX53 Quick Start
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3.8. LVDS   Video   Output   (J9)  
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The ? LVDS ? module ? of ? the ? i.MX53 ? Processor ? is ? connected ? to ? a ? 30 ‐ pin ? LVDS ? connector. ? While ? the ? i.MX53 ?
Processor ? is ? capable ? of ? outputting ? to ? two ? separate ? LVDS ? displays, ? only ? one ? connector ? is ? pinned ? out ? on ?
the ? Quick ? Start ? board. ? The ? pin ? outs ? on ? the ? LVDS ? connector ? match ? the ? optional ? cable ? and ? 10” ? HannStar ?
LVDS ? display ? that ? can ? be ? purchased ? optionally ? from ? Freescale. ? The ? single ? LVDS ? connector ? will ? support ?
video ? formats ? up ? to ? 165 ? Mega ‐ Pixels ? per ? second. ? The ? power ? source ? for ? the ? LVDS ? module ? is ? a ? switchable ?
output ? of ? the ? VBUCKPERI ? DCDC ? converter. ? This ? rail ? is ? shared ? with ? the ? SATA ? module ? and ? the ? USB ? module. ?
If ? these ? modules ? are ? not ? being ? used, ? the ? PMIC ? can ? be ? programmed ? to ? turn ? off ? power ? to ? these ? three ?
modules ? without ? affecting ? other ? 2.5V ? supplies ? to ? the ? remainder ? of ? the ? i.MX53 ? Applications ? Processor. ?
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3.9. Ethernet   (J2B)  
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The ? i.MX53 ? Processor ? Fast ? Ethernet ? Module ? outputs ? RMII ? formatted ? signals ? to ? an ? external ? Ethernet ? PHY. ?
The ? processor ? is ? capable ? of ? 10/100 ? Base ‐ T ? speeds. ? The ? Quick ? Start ? board ? uses ? the ? SMSC ? LAN8720A ?
Ethernet ? Transceiver ? in ? a ? QFN ‐ 24 ? package. ? 3.2V ? power ? is ? supplied ? to ? the ? Ethernet ? IC ? from ? the ? external ?
LDO ? regulator. ? The ? output ? of ? the ? Ethernet ? PHY ? is ? connected ? to ? an ? RJ45 ? jack ? with ? integrated ? magnetic. ?
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3.10. Dual   USB   Host   Connector   (J2A)  
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The ? USB ? module ? of ? the ? i.MX53 ? Processor ? provides ? two ? high ? speed ? USB ? PHYs ? that ? are ? connected ? to ? each ?
of ? the ? USB ‐ A ? Host ? Jacks ? on ? connector ? J2. ? One ? PHY ? provides ? Host ‐ only ? functionality ? and ? is ? connected ? to ?
the ? upper ? USB ? jack ? on ? the ? connector ? tower. ? The ? second ? PHY ? is ? USB ? 2.0 ? OTG ? capable ? and ? is ? connected ? to ?
the ? lower ? USB ? jack ? on ? the ? connector ? tower. ? Both ? jacks ? receive ? 5V ? power ? directly ? from ? the ? 5V ? Wall ?
Power ? Supply, ? via ? a ? FET ? that ? can ? be ? controlled ? by ? software, ? and ? a ? 1.1A ? Poly ‐ fuse. ? The ? PMIC ? provides ? an ?
over ‐ voltage ? functionality ? to ? limit ? voltage ? applied ? to ? the ? USB ? jack ? in ? the ? event ? that ? a ? DC ? Power ? Supply ?
other ? than ? the ? original ? supply ? provided ? is ? used. ? Also, ? there ? is ? no ? current ? regulating ? device ? to ? limit ?
current ? supplied ? to ? each ? jack, ? other ? than ? the ? Poly ‐ fuse. ?
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NOTE ?
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The ? lower ? USB ? Host ? Jack ? is ? cross ? connected ? with ? the ? Micro ‐ B ? USB ? Device ? connector. ? This ? was ? done ? as ? a ?
convenience ? to ? the ? user ? as ? cables ? with ? micro ‐ A ? plugs ? are ? still ? uncommon ? at ? the ? time ? the ? board ? was ?
designed. ? The ? USB ? OTG ? PHY ? will ? switch ? to ? ‘device’ ? mode ? if ? a ? USB ? Host ? is ? attached ? to ? the ? micro ‐ B ?
connector ? with ? a ? cable. ? This ? design ? is ? not ? recommended ? for ? release ? to ? the ? general ? electronics ? consumer ?
population. ? This ? board ? has ? not ? been ? tested ? for ? USB ? compliance. ?
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Freescale Semiconductor
Hardware User Guide for i.MX53 Quick Start Board,
Preliminary Rev 0.91
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PUBI – Public Use Business Information ?
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